Computer architecture Study Guide

📖 Core Concepts Computer Architecture – Structured design of a computer system; the “blue‑print” that defines how components work together, independent of low‑level implementation details. Instruction Set Architecture (ISA) – The programmer‑visible machine code (word size, registers, addressing modes, data types). It is the software/hardware interface. Microarchitecture – The concrete implementation of an ISA (pipeline depth, cache sizes, execution units). Macroarchitecture – Higher‑level abstract layers above microarchitecture that expose a consistent programmer view across different ISAs. Performance vs. Power – Design must balance speed (throughput, latency) with energy use; modern focus is on performance‑per‑watt rather than raw clock speed. Implementation Stages – ISA → Microarchitecture → Logic design (gate level) → Circuit design (transistor level) → Physical layout (chip floorplan) → Validation (FPGA prototypes, emulators). --- 📌 Must Remember ISA = software‑hardware contract. Compilers translate high‑level code into ISA‑encoded binary instructions. IPC (Instructions Per Cycle) is a key efficiency metric; superscalar CPUs aim for 3–5 IPC by issuing multiple instructions each clock. Clock speed ≠ performance. GHz alone ignores IPC, memory latency, and pipeline depth. Pipelining: ↑ Throughput, ↓ Latency. Power‑Performance Trade‑off: Reducing power while keeping acceptable performance is a primary design goal; measured by performance‑per‑watt or energy‑per‑instruction. Real‑time requirement: Low interrupt latency is mandatory for systems like anti‑lock brakes. Moore’s Law slowdown → Shift from frequency scaling to power‑efficient, smaller designs. --- 🔄 Key Processes Design Flow Define ISA → 2. Specify microarchitecture → 3. Create gate‑level logic → 4. Map to transistor‑level circuits → 5. Lay out physical chip → 6. Validate with emulators / FPGA prototypes. Performance Evaluation Measure IPC → Combine with clock frequency to estimate instructions per second. Run benchmarks → Obtain execution time for a suite → Identify workload‑specific strengths/weaknesses. Power‑Efficiency Evaluation Compute Performance‑per‑Watt = (Performance metric) / (Power consumption). Compute Energy‑per‑Instruction = (Power × Clock period) / IPC. --- 🔍 Key Comparisons ISA vs. Microarchitecture ISA: defines what instructions exist and their binary encoding. Microarchitecture: defines how those instructions are executed (pipeline, caches, ALUs). Clock Speed vs. IPC Higher clock → more cycles per second but does not guarantee more work if IPC is low. High IPC can offset a modest clock frequency. Latency vs. Throughput Latency: time for a single instruction to finish (affected negatively by deep pipelines). Throughput: number of instructions completed per unit time (improved by pipelining, superscalar issue). --- ⚠️ Common Misunderstandings “Higher GHz = faster CPU.” – Ignores IPC and other bottlenecks; a 2 GHz superscalar may outperform a 3 GHz scalar. “More transistors always improve performance.” – Extra transistors increase total power and heat; without efficient use they can degrade performance per watt. “ISA changes require new hardware.” – Microcode can adapt an existing chip to support new or multiple ISAs. “Benchmarks give absolute performance.” – Benchmarks reflect specific workloads; they may mislead for general‑purpose tasks. --- 🧠 Mental Models / Intuition “CPU as a factory” – ISA = product specification; microarchitecture = factory floor layout (assembly line, workers, storage). Faster line (higher IPC) can produce more even if the clock (shifts per hour) stays the same. Power‑Performance Trade‑off – Think of a car: more horsepower (performance) uses more fuel (power). Modern designs aim for better miles per gallon (performance‑per‑watt). Pipelining – Like a relay race: each runner (pipeline stage) works simultaneously, boosting overall speed (throughput) but the baton (instruction) still takes time to travel the whole track (latency). --- 🚩 Exceptions & Edge Cases Superscalar limits: Not all instruction streams can be parallelized; data dependencies and branch mispredictions reduce achievable IPC. Real‑time systems: May deliberately choose a simpler, deterministic microarchitecture (e.g., in‑order execution) to guarantee low latency despite lower peak throughput. Microcode flexibility: Some CPUs can support multiple ISAs via microcode, but performance may suffer compared to native implementations. --- 📍 When to Use Which Choose ISA design when you need software compatibility across many implementations (e.g., RISC‑V for open‑source ecosystems). Select microarchitectural features (large caches, deep pipelines) for workloads with high data locality and instruction-level parallelism (multimedia, scientific computing). Prefer in‑order, low‑latency pipelines for real‑time embedded controllers where predictability outweighs raw throughput. Use performance‑per‑watt benchmarks when evaluating mobile or data‑center CPUs where energy cost dominates. --- 👀 Patterns to Recognize High IPC + modest GHz → Likely superscalar, deep pipelines, good out‑of‑order execution. Low IPC + high GHz → Simple scalar pipeline, possibly power‑efficient design for embedded use. Benchmarks favoring specific workloads → Indicates specialized microarchitectural optimizations (e.g., large SIMD units for graphics). Power‑density spikes in newer nodes → Expect thermal throttling or need for advanced cooling. --- 🗂️ Exam Traps Trap: “The processor with the highest clock speed is always the fastest.” – Wrong; ignore IPC and architectural enhancements. Trap: “More transistors = better performance.” – Overlooks power‑density and diminishing returns. Trap: “Pipelining always reduces execution time.” – It improves throughput but can increase latency and suffer from stalls. Trap: “Benchmarks give a universal ranking.” – They are workload‑specific; a CPU that scores high on a graphics benchmark may be mediocre for database workloads. ---