Microcontroller Study Guide

📖 Core Concepts Microcontroller – a single‑chip computer that combines a processor core, program & data memory, and programmable I/O peripherals. Harvard architecture – separate buses for instructions and data, allowing simultaneous fetch and read/write. Program memory types – NOR flash (field‑erasable), mask‑programmed ROM, ferroelectric RAM (FeRAM). Data memory – on‑chip RAM for runtime data; may also include EEPROM or non‑volatile RAM for persistent storage. Interrupt – a hardware signal that pauses the current instruction stream, saves context, runs an ISR, then restores context. Low‑power operation – sleep mode can drop current to nanowatts; wake‑up is typically interrupt‑driven. Peripheral blocks – GPIO, ADC, DAC, timers, PWM, UART, SPI, I²C, USB, Ethernet, etc., all configurable in software. Interrupt latency – the time from interrupt request to first ISR instruction; kept low & predictable by minimizing context save, using shadow registers, and allowing nesting. --- 📌 Must Remember All‑in‑one: CPU + memory + I/O on one die → size & cost reduction. Flash dominates modern firmware storage; mask ROM and one‑time PROM are legacy. Sleep current can be as low as nanowatts, enabling years of battery life. Interrupt sources: timer overflow, ADC completion, pin change, communication reception. Harvard advantage: parallel instruction fetch & data access → higher throughput. Common families: ARM Cortex‑M (most popular), Atmel AVR/AVR32, Microchip PIC (8‑, 16‑, 32‑bit), NXP LPC series. Interrupt latency tricks: fewer saved registers, shadow registers, hardware atomic ops, nesting. --- 🔄 Key Processes Interrupt handling Detect interrupt request → CPU finishes current instruction. Save necessary registers (or switch to shadow registers). Jump to ISR address. Execute ISR (clear interrupt flag, perform quick task). Restore registers → resume pre‑interrupt code. Low‑power sleep/wake Enter sleep: halt CPU clock & most peripherals. Enable wake‑up sources (e.g., timer, pin change). Interrupt occurs → hardware exits sleep, restores clock, services ISR. Peripheral configuration (GPIO example) Set pin direction (input vs output). If input → enable pull‑up/down as needed, read digital level. If output → write high/low, optionally enable PWM for analog‑like control. ADC conversion Select channel, start conversion, wait for completion flag/interrupt, read result register. --- 🔍 Key Comparisons Microcontroller vs General‑purpose PC – MCUs: integrated CPU+memory+I/O, low power, no OS; PCs: separate components, high performance, multitasking OS. Flash vs EEPROM – Flash: large, block‑erase, used for program storage; EEPROM: byte‑addressable, slower, ideal for small persistent data. Harvard vs Von Neumann – Harvard: separate instruction/data buses → parallel fetch; Von Neumann: shared bus → possible bottleneck. Interrupt nesting vs non‑nesting – Nesting: higher‑priority ISR can pre‑empt a lower‑priority one (lower latency for critical events); non‑nesting: ISR runs to completion before any other interrupt. --- ⚠️ Common Misunderstandings “Unlimited on‑chip memory” – MCUs have strict program‑memory limits; external memory adds cost and complexity. “Interrupts are always faster than polling” – Polling can be acceptable for low‑frequency events; interrupt overhead (context save) may outweigh benefits if events are frequent. “All MCUs use Harvard architecture” – Some low‑cost MCUs still use Von Neumann. “Sleep mode always means nanowatt current” – Only specific low‑power families achieve nanowatt; others may still draw µA‑level currents. --- 🧠 Mental Models / Intuition Microcontroller = tiny, self‑contained computer – think of it as a smartphone’s brain stripped down to the essentials. Interrupt = doorbell – it rings, you pause what you’re doing, answer the door (ISR), then go back. Harvard bus = two‑lane highway – one lane for instructions, one for data, so traffic (fetches) never collides. --- 🚩 Exceptions & Edge Cases Some modern MCUs embed a floating‑point unit (FPU) or DSP‑optimized instructions (not universal). External EEPROM/Flash may be required when on‑chip storage is insufficient. Certain ultra‑low‑cost parts still rely on mask‑ROM or one‑time programmable memory for firmware. Shadow registers are not available on every architecture; latency reduction then depends on software‑optimized context saving. --- 📍 When to Use Which Flash vs EEPROM – Use flash for program code; use EEPROM (or FRAM) for small, frequently updated configuration data. ARM Cortex‑M vs AVR/PIC – Choose Cortex‑M for higher performance, richer peripheral sets, and better low‑power features; choose AVR/PIC for ultra‑low cost or legacy designs. Interrupt vs Polling – Use interrupt when event latency matters or CPU must sleep; use polling for simple, slow‑changing signals where ISR overhead is unnecessary. Harvard‑based MCU vs Von Neumann MCU – Prefer Harvard when you need maximum instruction throughput (e.g., DSP tasks); Von Neumann is acceptable for low‑speed control loops. --- 👀 Patterns to Recognize PWM block present → likely motor or LED dimming control. ADC channel configured → sensor input (temperature, light, potentiometer). UART/SPI/I²C blocks enabled → communication with external modules (GPS, flash, display). Sleep + enabled interrupt → design aimed at battery‑operated, event‑driven operation. Shadow registers / atomic instructions → design emphasizes deterministic interrupt latency. --- 🗂️ Exam Traps “All microcontrollers use a Von Neumann architecture.” – Many modern MCUs (e.g., Cortex‑M) use Harvard; the statement is false. “Interrupt latency is only about speed.” – Exam may emphasize predictability; low latency alone isn’t enough for real‑time guarantees. “Sleep mode always consumes nanowatts.” – Only specific low‑power families achieve that; most sleep currents are higher. “Every microcontroller has a built‑in floating‑point unit.” – Only some high‑end MCUs include an FPU; most rely on software emulation. “EEPROM can be erased with the same speed as flash.” – EEPROM erases at byte level and is slower; flash erases in blocks. ---