Embedded system Study Guide

📖 Core Concepts Embedded system – a dedicated computer (processor + memory + I/O) that performs a single function inside a larger device. Firmware – permanent program stored in ROM/flash that runs on the hardware. Real‑time constraint – a deadline that must be met for correct, safe operation (hard vs. soft). Microcontroller vs. microprocessor – MCU: processor, RAM, ROM, peripherals on one chip; MP: processor only, external chips required. Watchdog timer – hardware timer that forces a reset if the software fails to “kick” it periodically. MISRA C – a set of coding rules for C/C++ that eliminates unsafe constructs and improves reliability. --- 📌 Must Remember Dedicated functionality → one task, not a general‑purpose OS. Real‑time requirement → meet deadline or system failure (hard) vs. performance degradation (soft). Microcontroller integration → CPU + RAM + ROM + I/O = single package. Watchdog rule – software must periodically reset the watchdog; otherwise the chip resets. MISRA C key goal – prevent undefined behavior, enforce explicit types, avoid dynamic memory, limit pointer arithmetic. Interrupt‑controlled flow – short ISR handles time‑critical events; main loop does background work. Preemptive multitasking – timer ISR switches threads → need semaphores/message queues for shared data. --- 🔄 Key Processes Boot → Firmware Load Power‑on → reset vector → fetch firmware from ROM/flash → initialize peripherals. Interrupt Handling Event triggers hardware line → CPU saves context → executes ISR → ISR clears interrupt flag → restore context. Watchdog Refresh Periodic task → write specific value to watchdog register → if missed → watchdog expires → hardware reset. Model‑Based Code Generation Build data‑flow/state‑chart → tool auto‑generates C code → compile → flash onto MCU. --- 🔍 Key Comparisons Microcontroller vs. General‑Purpose Microprocessor MCU: integrated memory & peripherals; low power; limited resources. MP: separate chips; higher performance; more flexibility. Interrupt‑Controlled vs. Cooperative Multitasking Interrupt: hardware‑driven, pre‑emptive, need fast ISR. Cooperative: tasks voluntarily yield; simpler, but one task can hog CPU. ASIC vs. FPGA ASIC: fixed, high‑volume, low unit cost, long NRE. FPGA: re‑configurable, higher unit cost, ideal for low‑volume or prototyping. --- ⚠️ Common Misunderstandings “Real‑time = fast” – not always; a system can be real‑time but run slowly as long as deadlines are met. “Interrupts guarantee instant response” – ISR latency includes interrupt masking, context save, and priority resolution. “MISRA C makes code faster” – it improves safety, not performance; extra checks may add overhead. “Watchdog eliminates all software bugs” – it only recovers from a frozen system; logic errors can still cause incorrect operation before reset. --- 🧠 Mental Models / Intuition “Embedded as a Black Box” – think of the MCU as a sealed box that only reacts to inputs (sensors) and produces outputs (actuators) on a strict schedule. “ISR as a quick handshake” – ISR must acknowledge the event and return fast; any long work belongs in the main loop or a deferred task. “Watchdog as a heartbeat monitor” – if the system’s “pulse” stops, the watchdog restarts it. --- 🚩 Exceptions & Edge Cases Soft real‑time – missing a deadline degrades QoS but does not cause catastrophic failure. Watchdog timeout settings – too short → false resets; too long → delayed recovery. MISRA “required” vs. “advisory” – some rules are mandatory; others can be justified with documented deviation. --- 📍 When to Use Which Choose MCU when you need low power, small footprint, and integrated peripherals. Choose MP + external chips for high‑performance DSP or graphics where resources exceed MCU limits. Use interrupt‑controlled architecture for time‑critical I/O (e.g., UART reception). Use cooperative multitasking for simple, low‑load applications where deterministic scheduling isn’t critical. Use preemptive multitasking when multiple tasks have comparable priority and you need OS‑level scheduling. Select ASIC for mass‑produced devices with stable, unchanging functionality. Select FPGA for prototypes, low‑volume, or designs requiring post‑silicon reconfiguration. --- 👀 Patterns to Recognize “ISR → flag → main‑loop poll” – common pattern to defer heavy processing. “Watchdog reset → system re‑initialization” – look for a reset handler that re‑establishes peripheral state. “State‑chart → generated C switch‑case” – model‑based tools often map states to a switch statement. “Peripheral address map → memory‑mapped I/O” – reads/writes to specific addresses control hardware. --- 🗂️ Exam Traps Choosing “general‑purpose processor” for a low‑cost sensor node – the correct answer is usually a microcontroller. Assuming “any missed deadline = hard failure” – many systems are soft real‑time; answer choices will highlight this nuance. MISRA rule “no goto” – a distractor might be “no loops”; the actual rule forbids goto because it creates unstructured flow. Watchdog description “prevents all hangs” – the trap is ignoring that the watchdog can only reset, not fix logic errors. Confusing FPGA with ASIC performance – FPGA typically slower and higher power; ASIC is faster and lower power at high volume. ---