Digital electronics Study Guide

📖 Core Concepts Digital signal – two (or more) distinct voltage levels representing binary 0 and 1. Logic gate – a Boolean function implemented with transistors (or historic valves) that maps input bits to output bits. Combinational vs. Sequential – combinational outputs depend only on current inputs; sequential outputs also depend on stored state (feedback). Synchronous system – state changes only on a clock edge; asynchronous systems react immediately to input changes. Register‑Transfer Logic (RTL) – data moves between groups of flip‑flops (registers) via buses and multiplexers under control of a state machine. CMOS – the dominant logic family; complementary MOS transistors give high density, low static power, and fast switching. Noise immunity – a digital level is valid as long as noise does not push the voltage across the logic‑threshold region. Nyquist‑Shannon theorem – to reconstruct an analog signal, sample at ≥ 2 × highest frequency. 📌 Must Remember Binary decision: 0 = low voltage, 1 = high voltage (exact levels depend on technology). Deal–Grove oxide growth: $x^{2}+A\,x=B\,t$ ( $x$ = oxide thickness, $t$ = time). Fan‑out: number of gate inputs a single output can drive without exceeding current limits (modern CMOS ≈ 10+). Clocked flip‑flop stores a bit only on a clock edge → defines synchronous state registers. Power‑MOSFET: MOSFET optimized for high current/voltage, used in supplies, motor drives, converters. Moore’s Law: transistor count roughly doubles every 2 years; billions of transistors per processor now standard. Error detection: add a parity bit; can detect (and sometimes correct) single‑bit errors. 🔄 Key Processes Designing a combinational circuit Write truth table → derive Boolean expression → minimize with Karnaugh map / Quine‑McCluskey → implement with gates or lookup tables. Building a synchronous state machine Define states → draw state diagram → encode states (binary) → create next‑state logic (combinational) → connect to flip‑flops (state register) → add clock. Asynchronous design check List all possible input change orders → compute minimum/maximum propagation delays → add self‑resynchronization (e.g., Muller C‑elements) to avoid hazards. Register‑transfer operation On each clock: multiplexed bus selects source → data loaded into destination register → control signals generated by micro‑programmed control unit. 🔍 Key Comparisons CMOS vs. TTL – CMOS: low static power, high density, slower switching than early TTL; TTL: higher static power, older technology. Synchronous vs. Asynchronous – Synchronous: predictable timing, easier design, limited by clock frequency; Asynchronous: potentially faster, but vulnerable to race conditions and hazards. Logic gate (gate‑level) vs. Lookup Table (LUT) – Gate‑level: fixed wiring, cheaper for high volume; LUT: re‑programmable, ideal for low‑volume or FPGA designs. ⚠️ Common Misunderstandings “Digital consumes less power than analog.” – Not always; digital can draw more power for the same task, especially at high switching rates. “More bits always means better accuracy.” – Quantization error decreases with bits, but only if noise remains below the new LSB threshold. “Asynchronous circuits are always faster.” – Speed is limited by the longest combinational path; poor timing analysis can cause glitches that slow or stall the circuit. 🧠 Mental Models / Intuition Binary as on/off switches – imagine each transistor as a tiny light‑switch; a gate is a network of switches that only lets current flow for specific switch patterns. State machine as a player‑piano roll – the micro‑program is a sequence of “notes” (control bits) that tells the hardware which “keys” (gates) to activate each clock tick. Noise margin – picture the voltage window for a valid “0” or “1”; as long as noise stays inside the window, the digital value is safe. 🚩 Exceptions & Edge Cases Metastability – when a flip‑flop’s input changes too close to the clock edge, the output may linger in an undefined region; solved with synchronizer chains. Glitches in combinational logic – due to differing path delays, a gate output may briefly toggle; mitigated by careful gate sizing or adding hazard‑free logic. Fan‑out limits – driving many inputs can exceed the output’s drive capability, causing voltage drop and timing errors. 📍 When to Use Which Choose CMOS for low‑power, high‑density designs (most modern ASICs/FGPA). Select LUT/FPGA when design flexibility or low production volume outweighs per‑unit cost. Use synchronous design for most CPU‑type or high‑reliability systems. Consider asynchronous only when ultra‑low latency is critical and timing analysis resources are available. Add parity / ECC for storage or communication where error detection/correction outweighs extra bits. 👀 Patterns to Recognize Repeated Boolean sub‑expressions → candidate for shared gate or LUT, reducing logic count. State‑machine loops with single‑bit transitions → often a counter or shift register. Long combinational paths → likely the critical path; look for opportunities to pipeline or add registers. Clock‑gating opportunities – blocks whose outputs are static for many cycles can have their clocks disabled to save power. 🗂️ Exam Traps “Digital circuits always have lower power than analog.” – exam may present a high‑frequency CMOS block; the correct answer notes higher dynamic power. Confusing fan‑out with fan‑in – be careful: fan‑out = outputs driven; fan‑in = number of inputs a gate can accept. Mis‑applying Nyquist theorem – some questions may give sampling rate < 2×max frequency; the trap is to think it’s sufficient; the correct answer: it will cause aliasing. Assuming all MOSFETs are identical – power MOSFETs have larger channel widths and different biasing; selecting the wrong type leads to inadequate current handling. --- All bullets are derived directly from the provided outline; no external information was added.