Circuit Study Guide

📖 Core Concepts Electrical circuit – a closed loop that provides a return path for electric current. Analog vs. Digital – analog uses continuous signal levels; digital uses discrete (high/low) levels. Electronic circuit – contains active (non‑linear) components capable of amplification, computation, or data transfer. Synchronous vs. Asynchronous – synchronous circuits change state on a global clock; asynchronous (self‑timed) circuits do not use a clock. Integrated circuit (IC) – many electronic circuits fabricated on a single semiconductor chip; mixed‑signal ICs combine analog and digital sections. Series vs. Parallel – series: same current flows through each element; parallel: same voltage across each element. Filter circuits – RC, RL, LC, and RLC networks that shape frequency response. Boolean circuit – mathematical model of digital logic using Boolean variables and gates. Magnetic circuit – a closed loop that carries magnetic flux, analogous to an electrical circuit. --- 📌 Must Remember Series rule: $I{\text{total}} = I{\text{each}}$, $V{\text{total}} = \sum Vi$. Parallel rule: $V{\text{total}} = V{\text{each}}$, $I{\text{total}} = \sum Ii$. RC low‑pass cutoff: $fc = \dfrac{1}{2\pi RC}$. RL high‑pass cutoff: $fc = \dfrac{R}{2\pi L}$. RLC resonant frequency: $f0 = \dfrac{1}{2\pi\sqrt{LC}}$. Synchronous circuit timing: state changes only on clock edges. Asynchronous circuit: no global clock; handshaking or hazard‑free design required. Mixed‑signal IC: contains both analog (e.g., ADC) and digital (e.g., microcontroller) blocks on the same die. --- 🔄 Key Processes Circuit analysis (basic): Identify nodes and loops. Apply Kirchhoff’s Current Law (KCL) at each node (sum of currents = 0). Apply Kirchhoff’s Voltage Law (KVL) around each independent loop (sum of voltages = 0). Designing a simple RC low‑pass filter: Choose $R$ and $C$ to set desired $fc$ using $fc = 1/(2\pi RC)$. Connect resistor in series with input, capacitor from output node to ground. Creating a synchronous digital block: Place flip‑flops for state storage. Connect all flip‑flops to a common clock line. Ensure setup and hold times are met. Building a mixed‑signal IC layout (high‑level): Partition analog and digital blocks to minimize noise coupling. Route analog signals over continuous ground planes; digital signals over separate planes with proper shielding. --- 🔍 Key Comparisons Analog vs. Digital: Analog – continuous amplitude, susceptible to noise, useful for representing real‑world signals. Digital – discrete levels (0/1), robust to noise, easy to store/manipulate. Series vs. Parallel: Series – same current, voltage divides. Parallel – same voltage, current divides. Synchronous vs. Asynchronous: Synchronous – global clock coordinates all state changes. Asynchronous – local handshaking, potentially lower power but higher design complexity. RC vs. RL vs. LC vs. RLC filters: RC – uses resistor & capacitor; low‑pass or high‑pass. RL – resistor & inductor; high‑pass or low‑pass (inductive). LC – inductor & capacitor; creates resonant tank (band‑pass/stop). RLC – combines all three; tunable bandwidth and Q‑factor. --- ⚠️ Common Misunderstandings “Current is the same in parallel circuits.” – Only voltage is common; currents split according to branch impedances. “Inductors block DC forever.” – After the transient, an ideal inductor behaves as a short circuit for steady‑state DC. “Asynchronous circuits are always faster.” – Without a clock they can avoid clock‑skew but may suffer from handshake latency and race conditions. “Mixed‑signal ICs eliminate all analog/digital interference.” – Layout and shielding are still crucial; noise can couple across the die. --- 🧠 Mental Models / Intuition Water‑pipe analogy: Voltage = water pressure, current = flow rate, resistance = pipe diameter. Series pipes share the same flow (current), parallel pipes share the same pressure (voltage). Filter as a “sieve”: RC low‑pass lets slow (low‑frequency) water droplets through, blocks fast (high‑frequency) droplets. Clock as a conductor’s baton: In synchronous designs, every flip‑flop follows the baton’s beat; asynchronous musicians listen to each other’s cues. --- 🚩 Exceptions & Edge Cases Ideal vs. real components: Real inductors have series resistance; real capacitors have leakage – affecting filter Q and cutoff. Non‑linear elements: Diodes, transistors break the linear superposition used in simple series/parallel analysis. High‑frequency PCB traces: At RF, traces act as transmission lines; simple series/parallel rules no longer hold. Magnetic circuits: Reluctance (analogous to resistance) can change with saturation; linear analysis only valid in unsaturated region. --- 📍 When to Use Which Choose RC filter when you need a simple low‑pass or high‑pass with modest roll‑off and inexpensive components. Choose RL filter for high‑frequency applications where inductors are readily available and capacitors are too large. Choose LC or RLC when you need a sharp resonance (band‑pass or band‑stop) and can tolerate larger component size. Use synchronous design when predictable timing, easy testing, and high clock speeds are priorities. Use asynchronous design for ultra‑low‑power or when clock distribution is impractical (e.g., in some ASICs). Select mixed‑signal IC when a system must process analog inputs (sensing) and perform digital computation on the same chip. --- 👀 Patterns to Recognize Series‑parallel reduction appears repeatedly: look for groups of resistors, capacitors, or inductors that share nodes. Cut‑off frequency formulas always involve the product of the two reactive components (RC, RL, LC). Resonance condition shows up when an LC (or RLC) loop is present – expect a peak in impedance at $f0 = 1/(2\pi\sqrt{LC})$. Clock edge dependencies in synchronous diagrams: any state change without a preceding clock symbol is likely an error. Boolean gate cascades – a chain of AND/OR gates can often be simplified with De Morgan’s laws. --- 🗂️ Exam Traps Misreading “parallel” as “series.” Distractor answers may swap the voltage/current rules. Remember: parallel = same voltage. Using $fc = 1/(2\pi RC)$ for an RL circuit. RL cutoff uses $R/L$, not $RC$. Assuming ideal components in magnetic circuits. Saturation changes reluctance; exam may include a “non‑linear” clause. Selecting synchronous when the question mentions “no global clock.” That points to asynchronous design. Confusing mixed‑signal with purely digital ICs. Mixed‑signal includes ADC/DAC blocks; ignore if only digital logic is described. Overlooking the effect of component tolerances on filter bandwidth. Slightly off values can shift $fc$; some questions test awareness of “real‑world” variations.